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rev: 1.10 9/2000 1/34 ? 2000, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs 881e 18/ 36 t - 11/11.5/ 100 /80/66 512k x 18 , 256k x 36 bytesafe? 8mb sync burst srams 100 mhz?66 mhz 3.3 v v dd 3.3 v and 2.5 v i/o 100-pin tqfp commercial temp industrial temp 1.10 9/2000features ? ft pin for user-configurable flow through or pipelined operation ? dual cycle deselect (dcd) operation ? ieee 1149.1 jtag-compatible boundary scan ? on-chip write parity checking; even or odd selectable ? 3.3 v +10%/ ? 5% core power supply ? 2.5 v or 3.3 v i/o supply ? lbo pin for linear or interleaved burst mode ? internal input resistors on mode pins allow floating mode pins ? default to interleaved pipeline mode ? byte write ( bw ) and/or global write ( gw ) operation ? common data inputs and data outputs ? clock control, registered, address, data, and control ? internal self-timed write cycle ? automatic power-down for portable applications ? 100-lead tqfp package functional description applications the gs 881e 18/ / 36 t is a 9,437,184 - bit high performance synchronous sram with a 2 - bit burst address counter. although of a type originally developed for level 2 cache applications supporting high performance cpus, the device now finds application in synchronous sram applications , ranging from dsp main store to networking chip set support. controls addresses, data i/os, chip enables ( e1 , e2 ), address burst control inputs ( adsp , adsc , adv ) and write control inputs ( bx , bw , gw ) are synchronous and are controlled by a positive - edge - triggered clock input (ck). output enable ( g ) and power down control (zz) are asynchronous inputs. burst cycles can be initiated with either adsp or adsc inputs. in burst mode, subsequent burst addresses are generated internally and are controlled by adv . the burst address counter may be configured to count in either linear or interleave order with the linear burst order ( lbo ) input. the burst function need not be used. new addresses can be loaded on every cycle with no degradation of chip performance. flow through/pipeline reads the function of the data output register can be controlled by the user via the ft mode pin (pin 14) . holding the ft mode pin low places the ram in flow through mode, causing output data to bypass the data output register. holding ft high places the ram in pipeline mode, activating the rising- edge-triggered data output register. dcd pipelined reads the gs 881e 18/ / 36 t is a dcd (dual cycle deselect) pipelined synchronous sram. scd (single cycle deselect) versions are also available. dcd srams pipeline disable commands to the same degree as read commands. dcd rams hold the deselect command for one full cycle and then begin turning off their outputs just after the second rising edge of clock. byte write and global write byte write operation is performed by using byte write enable ( bw ) input combined with one or more individual byte write signals ( bx ). in addition, global write ( gw ) is available for writing all bytes at one time, regardless of the byte write control inputs. bytesafe? parity functions the gs 881e 18/36 t features bytesafe data security functions. see detailed discussion following. sleep mode low power (sleep mode) is attained through the assertion (high) of the zz signal, or by stopping the clock (ck). memory data is retained during sleep mode. core and interface voltages the gs 881e 18/ /36 t operates on a 3.3 v power supply, and all inputs/outputs are 3.3 v- and 2.5 v-compatible. separate output power ( v ddq ) pins are used to decouple output noise from the internal circuit. - 11 - 11.5 - 100 - 80 - 66 pipeline 3-1-1-1 tcycle t kq i dd 10 ns 4.0 ns 225 ma 10 ns 4.0 ns 225 ma 10 ns 4.0 ns 225 ma 12.5 ns 4.5 ns 200 ma 15 ns 5.0 ns 185 ma flow through 2-1-1-1 t kq tcycle i dd 11 ns 15 ns 180 ma 11.5 ns 15 ns 180 ma 12 ns 15 ns 180 ma 14 ns 15 ns 175 ma 18 ns 20 ns 165 ma
rev: 1.10 9/2000 2/34 ? 2000 , giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs 881e 18/ 36 t - 11/11.5/ 100 /80/66 gs 881e 18 100-pin tqfp pinout 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 v ddq v ss dq b1 dq b2 v ss v ddq dq b3 dq b4 ft v dd dp v ss dq b5 dq b6 v ddq v ss dq b7 dq b8 dq b9 v ss v ddq v ddq v ss dq a8 dq a7 v ss v ddq dq a6 dq a5 v ss qe v dd zz dq a4 dq a3 v ddq v ss dq a2 dq a1 v ss v ddq l b o a 5 a 4 a 3 a 2 a 1 a 0 t m s t d i v s s v d d t d o t c k a 1 0 a 1 1 a 1 2 a 1 3 a 1 4 a 1 6 a 6 a 7 e 1 e 2 n c n c b b b a a 1 7 c k g w b w v d d v s s g a d s c a d s p a d v a 8 a 9 a 1 5 512k x 18 top view dq a9 a 18 nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
rev: 1.10 9/2000 3/34 ? 2000 , giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs 881e 18/ 36 t - 11/11.5/ 100 /80/66 gs 881e 36 100-pin tqfp pinout 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 v ddq v ss dq c4 dq c3 v ss v ddq dq c2 dq c1 ft v dd dp v ss dq d1 dq d2 v ddq v ss dq d3 dq d4 dq d5 v ss v ddq v ddq v ss dq b4 dq b3 v ss v ddq dq b2 dq b1 v ss qe v dd zz dq a1 dq a2 v ddq v ss dq a3 dq a4 v ss v ddq l b o a 5 a 4 a 3 a 2 a 1 a 0 t m s t d i v s s t d o t c k a 1 0 a 1 1 a 1 2 a 1 3 a 1 4 a 1 6 a 6 a 7 e 1 e 2 b d b c b b b a a 1 7 c k g w b w v d d v s s g a d s c a d s p a d v a 8 a 9 a 1 5 256k x 36 top view dq b5 dq b9 dq b7 dq b8 dq b6 dq a6 dq a5 dq a8 dq a7 dq a9 dq c7 dq c8 dq c6 dq d6 dq d8 dq d7 dq d9 dq c5 dq c9 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 v d d
rev: 1.10 9/2000 4/34 ? 2000 , giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs 881e 18/ 36 t - 11/11.5/ 100 /80/66 tqfp pin descriptio pin location symbol typ e description 37, 36 a 0 , a 1 i address field lsbs and address counter preset inputs 35, 34, 33, 32, 100, 99, 82, 81, 44, 45, 46, 47, 48, 49, 50 , 92 a 2 ?a 17 i address inputs 80 a 18 i address inputs 63, 62, 59, 58, 57, 56, 53, 52 68, 69, 72, 73, 74, 75, 78, 79 13, 12, 9, 8, 7, 6, 3, 2 18, 19, 22, 23, 24, 25, 28, 29 dq a1 ?dq a8 dq b1 ?dq b8 dq c1 ?dq c8 dq d1 ?dq d8 i/o data input and output pins ( x36 version) 51, 80, 1, 30 dq a9 , dq b9 , dq c9 , dq d9 i/o data input and output pins 58, 59, 62, 63, 68, 69, 72, 73, 74 8, 9, 12, 13, 18, 19, 22, 23, 24 dq a1 ?dq a9 dq b1 ?dq b9 i/o data input and output pins 51, 52, 53, 56, 57 75, 78, 79, 1, 2, 3, 6, 7 25, 28, 29, 30 nc ? no connect 16 dp i parity input; 1 = even, 0 = odd 66 qe o parity error out; open drain output 87 bw i byte write?writes all enabled bytes; active low 93, 94 b a , b b i byte write enable for dq a , dq b data i/os; active low 95, 96 b c , b d i byte write enable for dq c , dq d data i/os; active low ( x36 version) 95, 96 nc ? no connect (x18 version) 89 ck i clock input signal; active high 88 gw i global write enable?writes all bytes; active low 98 e 1 i chip enable; active low 97 e 2 i chip enable; active high 86 g i output enable; active low 83 adv i burst address counter advance enable; active low 84, 85 adsp , adsc i address strobe (processor, cache controller); active low
rev: 1.10 9/2000 5/34 ? 2000 , giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs 881e 18/ 36 t - 11/11.5/ 100 /80/66 64 zz i sleep mode control; active high 14 ft i flow through or pipeline mode; active low 31 lbo i linear burst order mode; active low 38 tms i scan test mode select 39 tdi i scan test data in 42 tdo o scan test data out 43 tck i scan test clock 15, 41, 65, 91 v dd i core power supply 5,10,17, 21, 26, 40, 55, 60, 67, 71, 76, 90 v ss i i/o and core ground 4, 11, 20, 27, 54, 61, 70, 77 v ddq i output driver power supply pin location symbol typ e description
rev: 1.10 9/2000 6/34 ? 2000 , giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs 881e 18/ 36 t - 11/11.5/ 100 /80/66 gs 881e 18/36 block diagram a1 a0 a0 a1 d0 d1 q1 q0 counter load d q d q register register d q register d q register d q register d q register d q register d q register d q r e g i s t e r d q r e g i s t e r a0?an lbo adv ck adsc adsp gw bw b a b b b c b d ft g zz power down control memory array 36 36 4 a q d dqx0?dqx9 dp parity qe parity encode compare 36 4 36 36 4 32 note: only x36 version shown for simplicity. 0 36 36 d q r e g i s t e r 4 e 1 e 2
rev: 1.10 9/2000 7/34 ? 2000 , giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs 881e 18/ 36 t - 11/11.5/ 100 /80/66 bytesafe ? parity functions this sram includes a write data parity check that checks the validity of data coming into the ram on write cycles. in flow through mode, write data errors are reported in the cycle following the data input cycle. in pipeline mode, write data errors ar e reported one clock cycle later. (see write parity error output timing diagram .) the data parity mode (dp) pin must be tied high to set the ram to check for even parity or low to check for odd parity. read data parity is not checked by the ram as data. validity is best established at the data?s destination. the parity error output is an open drain output and drives low to indica te a parity error. multiple parity error output pins may share a common pull-up resistor. write parity error output timing diagram bpr 1999.05.18 ck d in a d in b d in c d in d d in e tkq tlz dq qe f l o w t h r o u g h m o d e p i p e l i n e d m o d e tkq tlz dq qe d in a d in b d in c d in d d in e err a err a err c err c thz tkqx thz tkqx
rev: 1.10 9/2000 8/34 ? 2000 , giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs 881e 18/ 36 t - 11/11.5/ 100 /80/66 note: there are pull-up device s on the lbo , dp and ft pin s and a pull down device on the zz pin, so those input pins can be unconnected and the chip will operate in the default states as specified in the above table. burst counter sequences bpr 1999.05.18 mode pin functions mode name pin name state function burst order control lbo l linear burst h or nc interleaved burst output register control ft l flow through h or nc pipeline power down control zz l or nc active h standby, i dd = i sb bytesafe data parity control dp l check for odd parity h or nc check for even parity linear burst sequence note: the burst counter wraps to initial state on the 5th clock. i nterleaved burst sequence note: the burst counter wraps to initial state on the 5th clock. a[1:0] a[1:0] a[1:0] a[1:0] 1st address 00 01 10 11 2nd address 01 10 11 00 3rd address 10 11 00 01 4th address 11 00 01 10 a[1:0] a[1:0] a[1:0] a[1:0] 1st address 00 01 10 11 2nd address 01 00 11 10 3rd address 10 11 00 01 4th address 11 10 01 00
rev: 1.10 9/2000 9/34 ? 2000 , giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs 881e 18/ 36 t - 11/11.5/ 100 /80/66 byte write truth table notes: 1. all byte outputs are active in read cycles regardless of the state of byte write enable inputs. 2. byte write enable inputs b a , b b , b c , and/or b d may be used in any combination with bw to write single or multiple bytes. 3. all byte i/os remain high-z during all write operations regardless of the state of byte write enable inputs. 4. bytes ? c ? and ? d ? are only available on the x36 version . function gw bw b a b b b c b d notes read h h x x x x 1 read h l h h h h 1 write byte a h l l h h h 2, 3 write byte b h l h l h h 2, 3 write byte c h l h h l h 2, 3, 4 write byte d h l h h h l 2, 3, 4 write all bytes h l l l l l 2, 3, 4 write all bytes l x x x x x
rev: 1.10 9/2000 10/34 ? 2000 , giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs 881e 18/ 36 t - 11/11.5/ 100 /80/66 synchronous truth table operation address used state diagram key 5 e1 e2 2 (x36only) adsp adsc adv w 3 dq 4 deselect cycle, power down none x h x x l x x high-z deselect cycle, power down none x l f l x x x high-z deselect cycle, power down none x l f h l x x high-z read cycle, begin burst external r l t l x x x q read cycle, begin burst external r l t h l x f q write cycle, begin burst external w l t h l x t d read cycle, continue burst next cr x x h h l f q read cycle, continue burst next cr h x x h l f q write cycle, continue burst next cw x x h h l t d write cycle, continue burst next cw h x x h l t d read cycle, suspend burst current x x h h h f q read cycle, suspend burst current h x x h h f q write cycle, suspend burst current x x h h h t d write cycle, suspend burst current h x x h h t d notes: 1. x = don?t care, h = high, l = low. 2. for x36 version, e = t (true) if e2 = 1 ; e = f (false) if e2 = 0 . 3. w = t (true) and f (false) is defined in the byte write truth table preceding. 4. g is an asynchronous input. g can be driven high at any time to disable active output drivers. g low can only enable active drivers (shown as ?q? in the truth table above). 5. all input combinations shown above are tested and supported. input combinations shown in gray boxes need not be used to accompli sh basic synchronous or synchronous burst operations and may be avoided for simplicity. 6. tying adsp high and adsc low allows simple non-burst synchronous operations. see bold items above. 7. tying adsp high and adv low while using adsc to load new addresses allows simple burst operations. see italic items above.
rev: 1.10 9/2000 11/34 ? 2000 , giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs 881e 18/ 36 t - 11/11.5/ 100 /80/66 first write first read burst write burst read deselect r w cr cw x x w r r w r x x x s i m p l e s y n c h r o n o u s o p e r a t i o n s i m p l e b u r s t s y n c h r o n o u s o p e r a t i o n cr r cw cr cr simplified state diagram notes: 1. the diagram shows only supported (tested) synchronous state transitions. the diagram presumes g is tied low. 2. the upper portion of the diagram assumes active use of only the enable ( e1 and e2 ) and write ( b a , b b , b c , b d , bw , and gw ) control inputs , and that adsp is tied high and adsc is tied low. 3. the upper and lower portions of the diagram together assume active use of only the enable, write , and adsc control inputs , and assumes adsp is tied high and adv is tied low.
rev: 1.10 9/2000 12/34 ? 2000 , giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs 881e 18/ 36 t - 11/11.5/ 100 /80/66 first write first read burst write burst read deselect r w cr cw x x w r r w r x x x cr r cw cr cr w cw w cw simplified state diagram with g notes: 1. the diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of g . 2. use of ?dummy reads? (read cycles with g high) may be used to make the transition from read cycles to write cycles without passing through a deselect cycle. dummy read cycles increment the address counter just like normal read cycles. 3. transitions shown in grey tone assume g has been pulsed high long enough to turn the ram?s drivers off and for incoming data to meet data input set up time.
rev: 1.10 9/2000 13/34 ? 2000 , giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs 881e 18/ 36 t - 11/11.5/ 100 /80/66 note: permanent damage to the device may occur if the absolute maximum ratings are exceeded. operation should be restricted to recomme nded operating conditions. exposure to conditions exceeding the absolute maximum ratings, for an extended period of time, may affect reliability of this component. notes: 1. unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 2.75 v v ddq 2.375 v (i.e., 2.5 v i/o) and 3.6 v v ddq 3.135 v (i.e., 3.3 v i/o), and quoted at whichever condition is worst case. 2. this device features input buffers compatible with both 3.3 v and 2.5 v i/o drivers. 3. most speed grades and configurations of this device are of f ered in both commercial and industrial temperature ranges. the part number of industrial temperature range versions end the character ?i?. unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 4. input under/overshoot voltage must be ?2 v > vi < v dd +2 v with a pulse width not to exceed 20% tkc. absolute maximum ratings (all voltages reference to v ss ) symbol description value unit v dd voltage on v dd pins ?0.5 to 4.6 v v ddq voltage in v ddq pins ?0.5 to v dd v v ck voltage on clock input pin ?0.5 to 6 v v i/o voltage on i/o pins ?0.5 to v ddq +0.5 ( 4.6 v max.) v v in voltage on other input pins ?0.5 to v dd +0.5 ( 4.6 v max.) v i in input current on any pin +/?20 ma i out output current on any i/o pin +/?20 ma p d package power dissipation 1.5 w t stg storage temperature ?55 to 125 o c t bias temperature under bias ?55 to 125 o c recommended operating conditions parameter symbol min. typ. max. unit notes supply voltage v dd 3.135 3.3 3.6 v i/o supply voltage v ddq 2.375 2.5 v dd v 1 input high voltage v ih 1.7 ? v dd +0.3 v 2 input low voltage v il ?0.3 ? 0.8 v 2 ambient temperature (commercial range versions) t a 0 25 70 c 3 ambient temperature (industrial range versions) t a ?40 25 85 c 3
rev: 1.10 9/2000 14/34 ? 2000 , giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs 881e 18/ 36 t - 11/11.5/ 100 /80/66 note: these parameters are sample tested. notes: 1. junction temperature is a function of sram power dissipation, package thermal resistance, mounting board temperature, ambient. t emper- ature air flow, board density, and pcb thermal resistance. 2. scmi g-38-87 3. average thermal resistance between die and top surface, mil spec-883, method 1012.1 capacitance (t a = 25 o c , f = 1 mh z , v dd = 3.3 v) parameter symbol test conditions typ. max. unit input capacitance c in v in = 0 v 4 5 pf input/output capacitance c i/o v out = 0 v 6 7 pf package thermal characteristics rating layer board symbol max unit notes junction to ambient (at 200 lfm) single r q ja 40 c/w 1,2 junction to ambient (at 200 lfm) four r q ja 24 c/w 1,2 junction to case (top) ? r q jc 9 c/w 3 20% tkc v ss ? 2.0 v 50% v ss v ih undershoot measurement and timing overshoot measurement and timing 20% tkc v dd + 2.0 v 50% v dd v il
rev: 1.10 9/2000 15/34 ? 2000 , giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs 881e 18/ 36 t - 11/11.5/ 100 /80/66 notes: 1. include scope and jig capacitance. 2. test conditions as specified with output loading as shown in fig. 1 unless otherwise noted. 3. output load 2 for t lz , t hz , t olz and t ohz 4. device is deselected as defined by the truth table. ac test conditions parameter conditions input high level 2.3 v input low level 0.2 v input slew rate 1 v/ns input reference level 1.25 v output reference level 1.25 v output load fig. 1& 2 dc electrical characteristics parameter symbol test conditions min max input leakage current (except mode pins) i il v in = 0 to v dd ?1 ua 1 ua zz input current i in zz v dd 3 v in 3 v ih 0 v v in v ih ?1 ua ?1 ua 1 ua 300 ua mode pin input current i in m v dd 3 v in 3 v il 0 v v in v il ?300 ua ?1 ua 1 ua 1 ua output leakage current i ol output disable, v out = 0 to v dd ?1 ua 1 ua output high voltage v oh i oh = ? 8 ma, v ddq = 2.375 v 1.7 v ? output high voltage v oh i oh = ? 8 ma, v ddq = 3.135 v 2.4 v ? output low voltage v ol i ol = 8 ma ? 0.4 v dq vt = 1.25 v 50 w 30pf * dq 2.5 v output load 1 output load 2 225 w 225 w 5pf * * distributed test jig capacitance
rev: 1.10 9/2000 16/34 ? 2000 , giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs 881e 18/ 36 t - 11/11.5/ 100 /80/66 operating currents parameter test conditions symbol -11 -11.5 -100 -80 -66 unit 0 to 70c ?40 to 85c 0 to 70c ?40 to 85c 0 to 70c ?40 to 85c 0 to 70c ?40 to 85c 0 to 70c ?40 to 85c operating current device selected; all other inputs 3 v ih o r v il output open i dd pipeline 225 235 225 235 225 235 200 210 185 195 ma i dd flow-thru 180 190 180 190 180 190 175 185 165 175 ma standby current zz 3 v dd - 0.2v i sb pipeline 30 40 30 40 30 40 30 40 30 40 ma i sb flow-thru 30 40 30 40 30 40 30 40 30 40 ma deselect current device deselected; all other inputs 3 v ih or v il i dd pipeline 80 90 80 90 80 90 70 80 60 70 ma i dd flow-thru 65 75 65 75 65 75 55 65 50 60 ma
rev: 1.10 9/2000 17/34 ? 2000 , giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs 881e 18/ 36 t - 11/11.5/ 100 /80/66 ac electrical characteristics notes: 1. these parameters are sampled and are not 100% tested . 2. zz is an asynchronous signal. however, in order to be recognized on any given clock cycle, zz must meet the specified setup and hold times as specified above. parameter symbol - 11 - 11.5 - 100 - 80 - 66 unit min max min max min max min max min max pipeline clock cycle time tkc 10 ? 10 ? 10 ? 12.5 ? 15 ? ns clock to output valid tkq ? 4.0 ? 4.0 ? 4.0 ? 4.5 ? 5 ns clock to output invalid tkqx 1.5 ? 1.5 ? 1.5 ? 1.5 ? 1.5 ? ns clock to output in low-z tlz 1 1.5 ? 1.5 ? 1.5 ? 1.5 ? 1.5 ? ns flow- thru clock cycle time tkc 15.0 ? 15.0 ? 15.0 ? 15.0 ? 20 ? ns clock to output valid tkq ? 11.0 ? 11.5 ? 12.0 ? 14.0 ? 18 ns clock to output invalid tkqx 3.0 ? 3.0 ? 3.0 ? 3.0 ? 3.0 ? ns clock to output in low-z tlz 1 3.0 ? 3.0 ? 3.0 ? 3.0 ? 3.0 ? ns clock high time tkh 1.7 ? 1.7 ? 2 ? 2 ? 2.3 ? ns clock low time tkl 2 ? 2 ? 2.2 ? 2.2 ? 2.5 ? ns clock to output in high-z thz 1 1.5 4.0 1.5 4.2 1.5 4.5 1.5 4.5 1.5 4.8 ns g to output valid toe ? 4.0 ? 4.2 ? 4.5 ? 4.5 ? 4.8 ns g to output in low-z tolz 1 0 ? 0 ? 0 ? 0 ? 0 ? ns g to output in high-z tohz 1 ? 4.0 ? 4.2 ? 4.5 ? 4.5 ? 4.8 ns setup time ts 1.5 ? 2.0 ? 2.0 ? 2.0 ? 2.0 ? ns hold time th 0.5 ? 0.5 ? 0.5 ? 0.5 ? 0.5 ? ns zz setup time tzzs 2 5 ? 5 ? 5 ? 5 ? 5 ? ns zz hold time tzzh 2 1 ? 1 ? 1 ? 1 ? 1 ? ns zz recovery tzzr 20 ? 20 ? 20 ? 20 ? 20 ? ns
rev: 1.10 9/2000 18/34 ? 2000 , giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs 881e 18/ 36 t - 11/11.5/ 100 /80/66 ck adsp adsc adv gw bw wr2 wr3 wr1 wr1 wr2 wr3 tkc single write burst write t kl t kh ts th ts th ts th ts th ts th ts th ts th write specified byte for 2 a and all bytes for 2 b , 2 c & 2 d adv must be inactive for adsp write adsc initiated write adsp is blocked by e inactive a 0 ?a n b a ? b d dq a ?dq d write deselected wr1 wr2 wr3 write cycle timing e 1 ts th e 2 only sampled with adsp or adsc e 1 masks adsp deselected with e 2 g ts th d2 a d2 b d2 c d2 d d3 a d1 a hi-z ts th e 2
rev: 1.10 9/2000 19/34 ? 2000 , giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs 881e 18/ 36 t - 11/11.5/ 100 /80/66 q1 a q3 a q2 d q2c q2 b q2 a tkq tlz toe tohz tolz tkqx thz tkqx ck adsp adsc bw g gw adv burst read rd2 rd3 tkl ts th th ts th ts th adsc initiated read suspend burst single read adsp is blocked by e inactive a 0 ?a n b a ? b d tkh tkc ts th ts ts th dq a ?dq d rd1 hi-z suspend burst flow through read cycle timing th th e 1 masks adsp deselected with e 2 e 1 ts ts e 2 e 2 only sampled with adsp or adsc
rev: 1.10 9/2000 20/34 ? 2000 , giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs 881e 18/ 36 t - 11/11.5/ 100 /80/66 flow through read-write cycle timing ck adsp adv gw bw g q1 a d1 a q2 a q2 b q2c q2 d single read burst read toe tohz ts th ts th th ts th ts th tkh dq a ?dq d b a ? b d tkl tkc ts single write adsp is blocked by e inactive tkq ts th hi-z q2 a burst wrap around to it?s initial state wr1 e 1 ts ts th e 1 masks adsp e 2 only sampled with adsp and adsc th adsc ts th adsc initiated read rd1 wr1 rd2 ts th a 0 ?a n e 2
rev: 1.10 9/2000 21/34 ? 2000 , giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs 881e 18/ 36 t - 11/11.5/ 100 /80/66 pipelined dcd read cycle timing q1 a q3 a q2 d q2c q2 b q2 a tkq tlz toe tohz tolz tkqx thz tkqx ck adsp adsc bw g gw adv burst read rd2 rd3 tkl th th ts th th ts th ts th adsc initiated read suspend burst e 1 masks adsp e 2 only sampled with adsp or adsc single read adsp is blocked by e 1 inactive a 0 ?a n b a ? b d e 1 tkh tkc ts th ts ts th dq a ?dq d ts ts rd1 hi-z e 2
rev: 1.10 9/2000 22/34 ? 2000 , giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs 881e 18/ 36 t - 11/11.5/ 100 /80/66 pipelined dcd read-write cycle timing ck adsp adv gw bw e 1 g wr1 q1 a d1a q2 a q2 b q2c q2 d single read burst read toe tohz ts ts th ts th ts th th ts th ts th tkh e 1 masks adsp e 2 only sampled with adsp and adsc dq a ?dq d tkl tkc ts th single write adsp is blocked by e 1 inactive tkq ts th hi-z b a ? b d adsc ts th adsc initiated read rd1 wr1 rd2 ts th a 0 ?a n e 2
rev: 1.10 9/2000 23/34 ? 2000 , giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs 881e 18/ 36 t - 11/11.5/ 100 /80/66 application tips single and dual cycle deselect scd devices force the use of ?dummy read cycles? (read cycles that are launched normally but that are ended with the output drivers inactive) in a fully synchronous environment. dummy read cycles waste performance but their use usually assures there will be no bus contention in transitions from reads to writes or between banks of rams. dcd srams do not waste bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at bank addres s boundary crossings) but greater care must be exercised to avoid excessive bus contention. jtag port operation overview the jtag port on this ram operates in a manner consistent with ieee standard 1149.1-1990, a serial boundary scan interface standard (commonly referred to as jtag), but does not implement all of the functions required for 1149.1 compliance. some functions have been modified or eliminated because they can slow the ram. nevertheless, the ram supports 1149.1-1990 tap (test access port) controller architecture, and can be expected to function in a manner that does not conflict with the operatio n of standard 1149.1 compliant devices. the jtag port interfaces with conventional ttl / cmos logic level signaling. disabling the jtag port it is possible to use this device without utilizing the jtag port. the port is reset at power-up and will remain inactive unless clocked. tck, tdi, and tms are designed with internal pull-up circuits. to assure normal operation of the ram with the jtag port unused, tck, tdi, and tms may be left floating or tied to either v dd or v ss . tdo should be left unconnected. ck adsp adsc th tkh tkl tkc ts zz tzzr tzzh tzzs ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ snooze sleep mode timing diagram
rev: 1.10 9/2000 24/34 ? 2000 , giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs 881e 18/ 36 t - 11/11.5/ 100 /80/66 jtag port registers overview the various jtag registers, refered to as tap registers, are selected (one at a time) via the sequences of 1s and 0s applied to tms as tck is strobed. each of the tap registers are serial shift registers that capture serial input data on the rising edge of tck and push serial data out on the next falling edge of tck. when a register is selected it is placed between the tdi and tdo pins. instruction register the instruction register holds the instructions that are executed by the tap controller when it is moved into the run, test/idle or the various data register states. instructions are 3 bits long. the instruction register can be loaded when it is placed between the tdi and tdo pins. the instruction register is automatically preloaded with the idcode instruction at power-up or whenever the controller is placed in test-logic-reset state. bypass register the bypass register is a single-bit register that can be placed between tdi and tdo. it allows serial test data to be passed thr ough the rams jtag port to another device in the scan chain with as little delay as possible. boundary scan register boundary scan register is a collection of flip flops that can be preset by the logic level found on the ram?s input or i/o pins. the flip flops are then daisy chained together so the levels found can be shifted serially out of the jtag port?s tdo pin. the boundary scan register also includes a number of place holder flip flops (always set to a logic 1). the relationship between th e device pins and the bits in the boundary scan register is described in the scan order table following. the boundary scan register, under the control of the tap controller, is loaded with the contents of the rams i/o ring when the controller is in capture-dr state and then is placed between the tdi and tdo pins when the controller is moved to shift-dr state. two tap instructions can be used to activate the boundary scan register. jtag pin descriptions pin pin name i/o description tck test clock in clocks all tap events. all inputs are captured on the rising edge of tck and all outputs propagate from the falling edge of tck. tms test mode select in the tms input is sampled on the rising edge of tck. this is the command input for the tap controller state machine. an undriven tms input will produce the same result as a logic one input level. tdi test data in in the tdi input is sampled on the rising edge of tck. this is the input side of the serial registers placed between tdi and tdo. the register placed between tdi and tdo is determined by the state of the tap controller state machine and the instruction that is currently loaded in the tap instruction register (refer to the tap controller state diagram). an undriven tdi pin will produce the same result as a logic one input level. tdo test data out out output that is active depending on the state of the tap state machine. output changes in response to the falling edge of tck. this is the output side of the serial registers placed between tdi and tdo. note: this device does not have a trst (tap reset) pin. trst is optional in ieee 1149.1. the test-logic-reset state is entered while t ms is held high for five rising edges of tck. the tap controller is also reset automaticly at power-up.
rev: 1.10 9/2000 25/34 ? 2000 , giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs 881e 18/ 36 t - 11/11.5/ 100 /80/66 jtag tap block diagram identification (id) register the id register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in capture-dr state with the idcode command loaded in the instruction register. the code is loaded from a 32-bit on-chip rom. it describes various attributes of the ram as indicated below. the register is then placed between the tdi and tdo pins when the controller is moved into shift-dr state. bit 0 in the register is the lsb and the first to reach tdo when shifting begins. tap controller instruction set overview there are two classes of instructions defined in the standard 1149.1-1990; the standard (public) instructions, and device specif ic (private) instructions. some public instructions, are mandatory for 1149.1 compliance. optional public instructions must be implemented in prescribed ways. although the tap controller in this device follows the 1149.1 conventions, it is not 1194.1- compliant because some of the mandatory instructions are not fully implemented. the tap on this device may be used to monitor all input and i/o pads, but cannot be used to load address, data or control signals into the ram or to preload the i/o buffers.t his device will not perform extest, intest or the sample/preload command. when the tap controller is placed in capture-ir state the two least significant bits of the instruction register are loaded with 01. when the controller is moved to the shift-ir state the instruction register is placed between tdi and tdo. in this state the des ired id register contents die revision code not used i/o configuration gsi technology jedec vendor id code p r e s e n c e r e g i s t e r bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1 1 10 9 8 7 6 5 4 3 2 1 0 x36 x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 1 1 0 0 1 1 x18 x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 instruction register id code register boundary scan register 0 1 2 0 1 2 31 30 29 0 1 2 n 0 bypass register tdi tdo tms tck test access port (tap) controller
rev: 1.10 9/2000 26/34 ? 2000 , giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs 881e 18/ 36 t - 11/11.5/ 100 /80/66 instruction is serially loaded through the tdi input (while the previous contents are shifted out at tdo). for all instructions, the tap executes newly loaded instructions only when the controller is moved to update-ir state. the tap instruction set for this device is listed in the following table. jtag tap controller state diagram instruction descriptions bypass when the bypass instruction is loaded in the instruction register the bypass register is placed between tdi and tdo. this occurs when the tap controller is moved to the shift-dr state. this allows the board level scan path to be shortened to facilitate testing o f other devices in the scan path. sample/preload sample/preload is a standard 1149.1 mandatory public instruction. when the sample/preload instruction is loaded in the instruc- tion register, moving the tap controller into the capture-dr state loads the data in the rams input and i/o buffers into the bou ndary scan register. because the ram clock is independent from the tap clock (tck) it is possible for the tap to attempt to capture the i/o ring con- tents while the input buffers are in transition (i.e. in a metastable state). although allowing the tap to sample metastable inp uts will not harm the device, repeatable results cannot be expected. ram input signals must be stabilized for long enough to meet the taps input d ata cap- ture set-up plus hold time (tts plus tth ). the rams clock inputs need not be paused for any other tap operation except capturin g the i/o ring contents into the boundary scan register. moving the controller to shift-dr state then places the boundary scan register be tween the tdi and tdo pins. because the preload portion of the command is not implemented in this device, moving the controller to the upd ate- dr state with the sample / preload instruction loaded in the instruction register has the same effect as the pause-dr command. t his functionality is not standard 1149.1-compliant. select dr capture dr shift dr exit1 dr pause dr exit2 dr update dr select ir capture ir shift ir exit1 ir pause ir exit2 ir update ir test logic reset run test idle 0 0 1 0 1 1 0 0 1 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 1 1 1 1
rev: 1.10 9/2000 27/34 ? 2000 , giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs 881e 18/ 36 t - 11/11.5/ 100 /80/66 extest extest is an ieee 1149.1 mandatory public instruction. it is to be executed whenever the instruction register, whatever length i t may be in the device, is loaded with all logic 0s. extest is not implemented in this device. therefore, this device is not 1149.1-complian t. neverthe- less, this ram?s tap does respond to an all zeros instruction, as follows. with the extest (000) instruction loaded in the instr uction regis- ter the ram responds just as it does in response to the bypass instruction described above. idcode the idcode instruction causes the id rom to be loaded into the id register when the controller is in capture-dr mode and places the id register between the tdi and tdo pins in shift-dr mode. the idcode instruction is the default instruction loaded in at power up and any time the controller is placed in the test-logic-reset state. sample-z if the sample-z instruction is loaded in the instruction register, all ram outputs are forced to an inactive drive state (high-z ) and the boundary scan register is connected between tdi and tdo when the tap controller is moved to the shift-dr state. rfu these instructions are reserved for future use. in this device they replicate the bypass instruction. jtag tap instruction set summary instruction code description notes extest 000 replicates bypass instruction. places bypass register between tdi and tdo. this ram does not implement 1149.1 extest function. *not 1149.1 compliant * 1 idcode 001 preloads id register and places it between tdi and tdo. 1, 2 sample-z 010 captures i/o ring contents. places the boundary scan register between tdi and tdo. forces all ram output drivers to high-z. 1 rfu 011 do not use this instruction; reserved for future use. replicates bypass instruction. places bypass register between tdi and tdo. 1 sample/ preload 100 captures i/o ring contents. places the boundary scan register between tdi and tdo. this ram does not implement 1149.1 preload function. *not 1149.1 compliant * 1 gsi 101 gsi private instruction. 1 rfu 110 do not use this instruction; reserved for future use. replicates bypass instruction. places bypass register between tdi and tdo. 1 bypass 111 places bypass register between tdi and tdo. 1 notes: 1. instruction codes expressed in binary, msb on left, lsb on right. 2. default instruction automatically loaded at power-up and in test-logic-reset state.
rev: 1.10 9/2000 28/34 ? 2000 , giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs 881e 18/ 36 t - 11/11.5/ 100 /80/66 jtag port recommended operating conditions and dc characteristics parameter symbol min. max. unit notes test port input high voltage v iht 1.7 v dd +0.3 v 1, 2 test port input low voltage v ilt ?0.3 0.8 v 1, 2 tms, tck and tdi input leakage current i in th ?300 1 ua 3 tms, tck and tdi input leakage current i in tl ?1 1 ua 4 tdo output leakage current i olt ?1 1 ua 5 test port output high voltage v oht 2.4 ? v 6, 7 test port output low voltage v olt ? 0.4 v 6, 8 notes: 1. this device features input buffers compatible with both 3.3 v and 2.5 v i/o drivers. 2. input under/overshoot voltage must be ?2 v > vi < v dd +2 v with a pulse width not to exceed 20% ttkc. 3. v dd 3 v in 3 v il 4. 0 v v in v il 5. output disable, v out = 0 to v dd 6. the tdo output driver is served by the v dd supply. 7. i oh = ?4 ma 8. i ol = +4 ma notes: 1. include scope and jig capacitance. jtag port ac test conditions parameter conditions input high level 2.3 v input low level 0.2 v input slew rate 1 v/ns input reference level 1.25 v output reference level 1.25 v dq v t = 1.25 v 50 w 30pf * jtag port ac test load * distributed test jig capacitance
rev: 1.10 9/2000 29/34 ? 2000 , giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs 881e 18/ 36 t - 11/11.5/ 100 /80/66 jtag port timing diagram jtag port ac electrical characteristics parameter symbol min max unit tck cycle time ttkc 20 ? ns tck low to tdo valid ttkq ? 10 ns tck high pulse width ttkh 10 ? ns tck low pulse width ttkl 10 ? ns tdi & tms set up time tts 5 ? ns tdi & tms hold time tth 5 ? ns ttkq tts tth ttkh ttkl tck tms tdi tdo ttkc
rev: 1.10 9/2000 30/34 ? 2000 , giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs 881e 18/ 36 t - 11/11.5/ 100 /80/66 gs 81 1e 18/36t tqfp boundary scan register notes: 1. the boundary scan register contains a number of registers that are not connected to any pin. they default to the value shown at reset. 2. registers are listed in exit order (i.e. location 1 is the first out of the tdo pin. 3. nc = no connect, na = not active, ph = place holder (no associated pin) order x36 x18 pin 1 ph = 0 n/a 2 ph = 0 n/a 3 a 10 44 4 a 11 45 5 a 12 46 6 a 13 47 7 a 14 48 8 a 15 49 9 a 16 50 10 x36 = dq a9 nc = 1 51 11 dq a8 nc = 1 52 12 dq a7 nc = 1 53 13 dq a6 nc = 1 56 14 dq a5 nc = 1 57 15 dq a4 dq a1 58 16 dq a3 dq a2 59 17 dq a2 dq a3 62 18 dq a1 dq a4 63 19 zz 64 20 qe 66 21 dq b1 dq a5 68 22 dq b2 dq a6 69 23 dq b3 dq a7 72 24 dq b4 dq a8 73 25 dq b5 dq a9 74 26 dq b6 nc = 1 75 27 dq b7 nc = 1 78 28 dq b8 nc = 1 79 29 x36 = dq b9 a 18 80 30 a 9 81 31 a 8 82 32 adv 83 33 adsp 84 34 adsc 85 35 g 86 36 bw 87 37 gw 88 38 ck 89 39 ph = 0 n/a 40 ph = 0 n/a 41 a 17 92 42 b a 93 43 b b 94 44 b c nc = 1 95 45 b d nc = 1 96 46 e 2 97 47 e 1 98 48 a 7 99 49 a 6 100 50 x36 = dq c9 nc = 1 1 51 dq c8 nc = 1 2 52 dq c7 nc = 1 3 53 dq c6 nc = 1 6 54 dq c5 nc = 1 7 55 dq c4 dq b1 8 56 dq c3 dq b2 9 57 dq c2 dq b3 12 58 dq c1 dq b4 13 order x36 x18 pin 59 ft 14 60 dp 16 61 ph = 0 n/a 62 dq d1 dq b5 18 63 dq d2 dq b6 19 64 dq d3 dq b7 22 65 dq d4 dq b8 23 66 dq d5 dq b9 24 67 dq d6 nc = 1 25 68 dq d7 nc = 1 28 69 dq d8 nc = 1 29 70 x36 = dq d9 nc = 1 30 71 lbo 31 72 a 5 32 73 a 4 33 74 a 3 34 75 a 2 35 76 a 1 36 77 a 0 37 78 ph = 0 n/a bpr 1999.08.11 order x36 x18 pin
rev: 1.10 9/2000 31/34 ? 2000 , giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs 881e 18/ 36 t - 11/11.5/ 100 /80/66 output driver characteristics bpr 1999.05.18 -140.0 -120.0 -100.0 -80.0 -60.0 -40.0 -20.0 0.0 20.0 40.0 60.0 80.0 100.0 120.0 -0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 v out (pull down) vddq - v out (pull up) i out (ma) 3.6v pd hd 3.3v pd hd 3.1v pd hd 3.1v pu hd 3.3v pu hd 3.6v pu hd pull up drivers pull down drivers vddq vout i out vss
rev: 1.10 9/2000 32/34 ? 2000 , giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs 881e 18/ 36 t - 11/11.5/ 100 /80/66 tqfp package drawing bpr 1999.05.18 d 1 d e1 e p i n 1 b e c l l1 a2 a1 y q notes: 1. all dimensions are in millimeters (mm). 2. package width and length do not include mold protrusion. symbol description min. nom. max a1 standoff 0.05 0.10 0.15 a2 body thickness 1.35 1.40 1.45 b lead width 0.20 0.30 0.40 c lead thickness 0.09 ? 0.20 d terminal dimension 21.9 22.0 22.1 d1 package body 19.9 20.0 20.1 e terminal dimension 15.9 16.0 16.1 e1 package body 13.9 14.0 14.1 e lead pitch ? 0.65 ? l foot length 0.45 0.60 0.75 l1 lead length ? 1.00 ? y coplanarity ? ? 0.10 q lead angle 0 ? 7
rev: 1.10 9/2000 33/34 ? 2000 , giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs 881e 18/ 36 t - 11/11.5/ 100 /80/66 ordering information for gsi synchronous burst rams org part number 1 type package speed 2 (mhz/ns) t a 3 status 514k x 18 GS881E18T-11 bytesafe dcd pipeline/flow through tqfp 100/11 c 514k x 18 GS881E18T-11.5 bytesafe dcd pipeline/flow through tqfp 100/11.5 c 514k x 18 gs881e18t-100 bytesafe dcd pipeline/flow through tqfp 100/12 c 514k x 18 gs881e18t-80 bytesafe dcd pipeline/flow through tqfp 80/14 c 514k x 18 gs881e18t-66 bytesafe dcd pipeline/flow through tqfp 66/18 c 256k x 36 gs881e36t-11 bytesafe dcd pipeline/flow through tqfp 100/11 c 256k x 36 gs881e36t-11.5 bytesafe dcd pipeline/flow through tqfp 100/11.5 c 256k x 36 gs881e36t-100 bytesafe dcd pipeline/flow through tqfp 100/12 c 256k x 36 gs881e36t-80 bytesafe dcd pipeline/flow through tqfp 80/14 c 256k x 36 gs881e36t-66 bytesafe dcd pipeline/flow through tqfp 66/18 c 514k x 18 GS881E18T-11i bytesafe dcd pipeline/flow through tqfp 100/11 i 514k x 18 GS881E18T-11.5i bytesafe dcd pipeline/flow through tqfp 100/11.5 i 514k x 18 gs881e18t-100i bytesafe dcd pipeline/flow through tqfp 100/12 i 514k x 18 gs881e18t-80i bytesafe dcd pipeline/flow through tqfp 80/14 i 514k x 18 gs881e18t-66i bytesafe dcd pipeline/flow through tqfp 66/18 i 256k x 36 gs881e36t-11i bytesafe dcd pipeline/flow through tqfp 100/11 i 256k x 36 gs881e36t-11.5i bytesafe dcd pipeline/flow through tqfp 100/11.5 i 256k x 36 gs881e36t-100i bytesafe dcd pipeline/flow through tqfp 100/12 i 256k x 36 gs881e36t-80i bytesafe dcd pipeline/flow through tqfp 80/14 i 256k x 36 gs881e36t-66i bytesafe dcd pipeline/flow through tqfp 66/18 i notes: 1. customers requiring delivery in tape and reel should add the character ?t? to the end of the part number. example: gs 881e 18 t t. 2. the speed column indicates the cycle frequency (mhz) of the device in pipeline mode and the latency (ns) in flow through mode. each device is pipeline/flow through mode-selectable by the user. 3. t a = c = commercial temperature range. t a = i = industrial temperature range. 4. gsi offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. see the gsi technology web site ( www.gsitechnology.com ) for a complete listing of current offerings.
rev: 1.10 9/2000 34/34 ? 2000 , giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs 881e 18/ 36 t - 11/11.5/ 100 /80/66 revision history ds/daterev. code: old; new types of changes format or content page;revisions;reason gs 881e 18/36 t rev1.04h 5/ 1999; 1.05 9/1999i format/typos ? last page/fixed ?gsgs..? in ordering information note. ? fromatted pin outs and pin description to new small caps. ? formatted block diagrams to new small caps. ? formatted timing diagrams to new small caps. ? changed ?flow thru? to ?flow through? in timing diagrams. ? boundary scan register/formatted to new small caps. ? package diagram/changed ?dimesion? to ?dimension?. content ? 5/fixed pin description table to match pinouts. ? pin description/changed chip enables to match pins. ? pin description/changed pin 80 from nc to address input. ? pin description/rearranged address inputs to match order of pinout ? changed i to o for tdo ? package diagram/changed dimension d max from 20.1 to 22.1 ? gs 881e 18/36 t 1.05 9/ 1999i; 1.0 5 11/1999j content ? first release of 880 f. gs 881e 18/ 36 t 1.0 5 11/ 1999 k 881e 18/ 36 t 1.0 6 1/ 2000 10 l content ? changed order of tqfp address inputs to match pinout. ? changed order of tqfp data input and output pins to match pinout. ? new gsi logo. gs 881e 18/ 36 t 1.0 6 1/ 2000 l ; gs 881e 18/ 36 t 1.0 7 3/ 2000n; content ? changed all speed bin information (headings, references, tables, ordering info..) to reflect 150 - 80mhz gs 881e 18/ 36 t 1.0 7 3/ 2000 n ; gs 881e 18/ 36 t 1.0 8 3/ 2000o; content ? corrections to ac electrical characteristics table - ? fixed boundary scan register added pin 29 881e gs 881e 18/ 36 t 1.0 8 3/ 2000o; 88 1 e183236_r1_09 content/format ? removed 150 mhz speed bin ? changed 133 mhz and 117 mhz speed bins to 11 ns and 11.5 ns (100 mhz) numbers ? updated format to comply with technical publications standards 881e18_r1_09; 881e18_r1_10 content ? updated capitance table?removed input row and changed output row to i/o

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